1. Field of the Invention
This invention relates to digital data communication circuits, and more particularly to the operational verification of serial data communication circuits.
2. Description of the Relevant Art
Electronic devices typically communicate via electrical signals (e.g., voltage and/or current) driven upon electrical conductors (e.g., metal wires). Simultaneous transmission of multiple signals is accommodated by several wires routed in parallel (i.e., buses). Most computer systems have a modular architecture centered around a bus which serves as a shared communication link between system components. The two major advantages of shared buses over direct communication links between system components are versatility and low cost. By defining a standard interconnection scheme for a given bus, new devices may be easily connected to the bus. The cost of the bus is low because it is shared among the number of components connected to the bus.
Due to technological advances, the signal processing capabilities of more modern electronic devices (e.g., microprocessors) are outstripping the signal transfer capabilities of conventional parallel buses. To their detriment, parallel buses have physical limitations which place an upper limit on the rate at which information can be transferred over the bus. For example, the electrical characteristics and loading of each wire of a bus may vary, causing signals transmitted simultaneously upon the bus to be received at different times. Bus timing must take into consideration worst case delays, resulting in reduced data transfer rates of systems employing parallel buses.
A serial data path, on the other hand, is a direct communication link between a single transmitter and a single receiver. Such a serial data path typically includes a transmission medium connected between the transmitter and receiver. The transmission medium may be, for example, a differentially-driven pair of wires or a fiber-optic cable. In cases where the transmission medium is a pair of wires, the communication link (i.e., channel) has a defined electrical loading and is typically optimized for minimum signal delay. As a result, the rate at which electrical signals can be transferred over such a serial data path exceeds the data transfer rate of a common shared parallel bus.
Serial data transmitter/receiver devices (i.e., transceivers) typically include a transmitter which transmits serial data and a receiver which receives serial data. The transmitter typically receives an external clocking signal used to synchronize the generation of a serial data stream. The serial data stream contains enough information to recover the external clocking signal. The receiver typically recovers the clocking signal used to transmit the serial data from the serial data stream, and uses the clocking signal to recover the data from the serial data stream. Thus the receiver is synchronous to the clocking signal inherent within the incoming serial data stream and not to the external clocking signal received by the transmitter.
Serial data transceivers offering digital signal transmission rates exceeding 1 gigabit per second are now commercially available. The testing of such transceivers at their normal operating speeds, however, presents many technical challenges. For example, consider two serial data links between transceivers of two different devices: a first serial data link between a transmitter of a first device and a receiver of a second device, and a second serial data link between a transmitter of the second device and a receiver of the first device. Each device receives a different clocking signal used to transmit serial data. Since no two clocking signals produced by two different sources have exactly the same frequency, each transceiver must be able to transmit serial data at one frequency and receive serial data at another (slightly different) frequency.
Now consider an integrated communications circuit including two or more serial data transceivers. The ability of each transceiver to transmit data at one frequency and receive data at another (slightly different) frequency must be tested and verified. A straightforward testing approach would involve individual testing of each transceiver. A test apparatus including a comparable serial data transceiver would be required, and the time required to test the integrated communications circuit would be proportional to the number of serial data transceivers of the integrated communications circuit.
It would be beneficial to have a testing apparatus which reduces the time and costs associated with the testing of an integrated communications circuit having multiple serial data transceivers. It would also be advantageous to incorporate as much of the testing apparatus as possible within the integrated communications circuit during manufacture in order to facilitate subsequent testing.